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NXP Semiconductors /LPC800 /MRT /CTRL2

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Interpret as CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE_)INTEN 0 (REPEAT_INTERRUPT_MOD)MODE 0RESERVED

MODE=REPEAT_INTERRUPT_MOD, INTEN=DISABLE_

Description

MRT0 Control register. This register controls the MRT0 modes.

Fields

INTEN

Enable the TIMERn interrupt.

0 (DISABLE_): Disable.

1 (ENABLE_): Enable.
MODE

Selects timer mode.

0 (REPEAT_INTERRUPT_MOD): Repeat interrupt mode.

1 (ONE_SHOT_INTERRUPT_M): One-shot interrupt mode.

2 (ONE_SHOT_BUS_STALL_M): One-shot bus stall mode.

3 (RESERVED_): Reserved.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data